Monthly Trending Repositories of SystemVerilog on GitHub Mon, 10 Aug 2026 07:37:07 GMT https://mshibanami.github.io/GitHubTrendingRSS https://github.com/verilator/verilator <p>Verilator open-source SystemVerilog simulator and lint system</p><hr> https://github.com/lowRISC/opentitan <p>OpenTitan: Open source silicon root of trust</p><hr> https://github.com/lowRISC/ibex <p>Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)</p><hr> https://github.com/openhwgroup/cvw <p>CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.</p><hr> https://github.com/chipsalliance/caliptra-rtl <p>HW Design Collateral for Caliptra RoT IP</p><hr> https://github.com/adam-maj/tiny-gpu <p>A minimal GPU design in Verilog to learn how GPUs work from the ground up</p><hr> https://github.com/chipsalliance/caliptra-ss <p>HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.</p><hr>