Monthly Trending Repositories of Verilog on GitHub Mon, 10 Aug 2026 04:37:21 GMT https://mshibanami.github.io/GitHubTrendingRSS https://github.com/The-OpenROAD-Project/OpenROAD <p>OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/</p><hr> https://github.com/YosysHQ/picorv32 <p>PicoRV32 - A Size-Optimized RISC-V CPU</p><hr> https://github.com/OSCPU/yosys-sta <p style="color:#586069;"><em>No description/README provided.</em></p> https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts <p>OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/</p><hr> https://github.com/EttusResearch/uhd <p>The USRP™ Hardware Driver Repository</p><hr> https://github.com/analogdevicesinc/hdl <p>HDL libraries and projects</p><hr> https://github.com/vortexgpgpu/vortex <p style="color:#586069;"><em>No description/README provided.</em></p> https://github.com/The-OpenROAD-Project/OpenSTA <p>OpenSTA engine</p><hr> https://github.com/OpenPOWERFoundation/a2o <p>The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.</p><hr>