Weekly Trending Repositories of SystemVerilog on GitHub Mon, 10 Aug 2026 07:37:28 GMT https://mshibanami.github.io/GitHubTrendingRSS https://github.com/verilator/verilator <p>Verilator open-source SystemVerilog simulator and lint system</p><hr> https://github.com/chipsalliance/caliptra-rtl <p>HW Design Collateral for Caliptra RoT IP</p><hr> https://github.com/chipsalliance/caliptra-ss <p>HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.</p><hr> https://github.com/lowRISC/opentitan <p>OpenTitan: Open source silicon root of trust</p><hr> https://github.com/chipsalliance/i3c-core <p style="color:#586069;"><em>No description/README provided.</em></p> https://github.com/pulp-platform/axi <p>AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication</p><hr> https://github.com/lowRISC/ibex <p>Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)</p><hr> https://github.com/chipsalliance/adams-bridge <p>Post-Quantum Cryptography IP Core (Crystals-Dilithium)</p><hr> https://github.com/lowRISC/ethernet <p>Open-source memory-mapped Ethernet MAC for FPGA with RGMII interface</p><hr> https://github.com/pulp-platform/riscv-dbg <p>RISC-V Debug Support for our PULP RISC-V Cores</p><hr> https://github.com/pulp-platform/fpu_div_sqrt_mvp <p>[UNRELEASED] FP div/sqrt unit for transprecision</p><hr> https://github.com/pulp-platform/axi_riscv_atomics <p>AXI Adapter(s) for RISC-V Atomic Operations</p><hr>